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Latency and energy aware value prediction for high-frequency processors.

, and . ICS, page 45-56. ACM, (2002)

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Improving Dynamic Cluster Assignment for Clustered Trace Cache Processors., and . ISCA, page 264-274. IEEE Computer Society, (2003)Latency and energy aware value prediction for high-frequency processors., and . ICS, page 45-56. ACM, (2002)The Role of Return Value Prediction in Exploiting Speculative Method-Level Parallelism., , and . J. Instruction-Level Parallelism, (2003)Evaluating MMX Technology Using DSP and Multimedia Applications., , , and . MICRO, page 37-46. ACM/IEEE Computer Society, (1998)Speculative path power estimation using trace-driven simulations during high-level design phase., , and . ICCD, page 630-637. IEEE Computer Society, (2016)Issues in the design of store buffers in dynamically scheduled processors., and . ISPASS, page 76-87. IEEE Computer Society, (2000)Rehashable BTB: An Adaptive Branch Target Buffer to Improve the Target Predictability of Java Code., , and . HiPC, volume 2552 of Lecture Notes in Computer Science, page 597-608. Springer, (2002)Improving Java performance using hardware translation., , and . ICS, page 427-439. ACM, (2001)Adapting branch-target buffer to improve the target predictability of java code., , and . ACM Trans. Archit. Code Optim., 2 (2): 109-130 (2005)Accelerating two-dimensional page walks for virtualized systems., , , and . ASPLOS, page 26-35. ACM, (2008)