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Delay Testing Quality in Timing-Optimized Designs., , , and . ITC, page 897-905. IEEE Computer Society, (1991)A weighted random pattern test generation system., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (8): 1020-1025 (1996)Effect of Record Length on Noise-Induced Error in the Cross Correlation Estimate., , and . IEEE Trans. Syst. Man Cybern., 2 (2): 255-261 (1972)Design of testable logic circuits.. Proc. IEEE, 74 (3): 525 (1986)Design for Testability: The Path to Deep Submicron.. Asian Test Symposium, IEEE Computer Society, (2005)Directed-Binary Search in Logic BIST Diagnostics., , and . DATE, page 1121. IEEE Computer Society, (2002)Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture., , , and . DATE, page 10110-10115. IEEE Computer Society, (2003)IDDQ Test: Sensitivity Analysis of Scaling., , , , and . ITC, page 786-792. IEEE Computer Society, (1996)On Efficiently and Reliably Achieving Low Defective Part Levels., , and . ITC, page 616-625. IEEE Computer Society, (1995)Fast seed computation for reseeding shift register in test pattern compression., , and . ICCAD, page 76-81. ACM / IEEE Computer Society, (2002)