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Fault Tolerance of Switch Blocks and Switch Block Arrays in FPGA.

, , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (7): 794-807 (2005)

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High-level aging estimation for FPGA-mapped designs., and . FPL, page 284-291. IEEE, (2012)FPGAhammer: Remote Voltage Fault Attacks on Shared FPGAs, suitable for DFA on AES., , and . IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018 (3): 44-68 (2018)A Comprehensive Framework for Parametric Failure Modeling and Yield Analysis of STT-MRAM., , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (7): 1697-1710 (2019)A Novel Printed-Lookup-Table-Based Programmable Printed Digital Circuit., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (6): 1496-1504 (2020)Reverse Engineering of Printed Electronics Circuits: From Imaging to Netlist Extraction., , , , and . IEEE Trans. Inf. Forensics Secur., (2020)Aging-Aware Design of Microprocessor Instruction Pipelines., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (5): 704-716 (2014)Instruction cache aging mitigation through Instruction Set Encoding., , , and . ISQED, page 325-330. IEEE, (2016)A-SOFT-AES: Self-adaptive software-implemented fault-tolerance for AES., , and . IOLTS, page 104-109. IEEE, (2013)An analytical approach for soft error rate estimation in digital circuits., and . ISCAS (3), page 2991-2994. IEEE, (2005)Application-dependent testing of FPGAs for bridging faults.. FPGA, page 248. ACM, (2003)