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Disambiguation of "Hassan, Hasan"

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Refresh Triggered Computation: Improving the Energy Efficiency of Convolutional Neural Network Accelerators.

, , , and . CoRR, (2019)

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Hassan Hasan

Istabrak Hasan

Mahamudul Hasan

Maen Khaled Amin Hasan

Alkomiet Hasan

 

Other publications of authors with the same name

Enabling Efficient RDMA-based Synchronous Mirroring of Persistent Memory Transactions., , , , , , , , , and 3 other author(s). CoRR, (2018)Understanding and Modeling On-Die Error Correction in Modern DRAM: An Experimental Study Using Real Devices., , , and . DSN, page 13-25. IEEE, (2019)Exploiting Row-Level Temporal Locality in DRAM to Reduce the Memory Access Latency., , , , , , and . CoRR, (2018)GRIM-Filter: Fast seed location filtering in DNA read mapping using processing-in-memory technologies., , , , , , , , , and . BMC Genom., (2018)Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics., , , , and . MICRO, page 282-297. IEEE, (2020)DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators., , , , , , , and . CoRR, (2022)MetaSys: A Practical Open-source Metadata Management System to Implement and Evaluate Cross-layer Optimizations., , , , , , , and . ACM Trans. Archit. Code Optim., 19 (2): 26:1-26:29 (2022)Refresh Triggered Computation: Improving the Energy Efficiency of Convolutional Neural Network Accelerators., , , and . ACM Trans. Archit. Code Optim., 18 (1): 2:1-2:29 (2021)DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips., , , , , , , , and . CoRR, (2022)HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips., , , , , , , and . MICRO, page 815-834. IEEE, (2022)