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Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices.

, , and . DATE, page 849-855. ACM, (2008)

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Implementation of a thermal management unit for canceling temperature-dependent clock skew variations., , , , , , and . Integr., 41 (1): 2-8 (2008)Performance analysis of 3-D monolithic integrated circuits., , , , , and . 3DIC, page 1-4. IEEE, (2010)Analysis and optimization of NBTI induced clock skew in gated clock trees., , , and . DATE, page 296-299. IEEE, (2009)Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective., , , , , , and . PATMOS, volume 4148 of Lecture Notes in Computer Science, page 214-224. Springer, (2006)Controlling NBTI degradation during static burn-in testing., and . ASP-DAC, page 597-602. IEEE, (2011)An integrated nonlinear placement framework with congestion and porosity aware buffer planning., , and . DAC, page 702-707. ACM, (2008)Thermal-Aware Clock Tree Design to Increase Timing Reliability of Embedded SoCs., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 57-I (10): 2741-2752 (2010)On stress aware active area sizing, gate sizing, and repeater insertion., and . ISPD, page 35-42. ACM, (2009)PASAP: power aware structured ASIC placement., and . ISLPED, page 395-400. ACM, (2010)Skew Management of NBTI Impacted Gated Clock Trees., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (6): 918-927 (2013)