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Finding the polygon hull of a network without conditions on the starting vertex.

, , , , and . Trans. Emerg. Telecommun. Technol., (2022)

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Menhir: Generic High-Speed FPGA Model-Checker., , and . DSD, page 65-72. IEEE, (2020)A prototyping platform for virtual reconfigurable units., , and . ReCoSoC, page 1-7. IEEE, (2014)PAnTHErS: A Prototyping and Analysis Tool for Homomorphic Encryption Schemes., , and . SECRYPT, page 359-366. SciTePress, (2017)Virtual SoPC rad-hardening for satellite applications., , , , , and . ReCoSoC, volume 7551 of KIT Scientific Reports, page 179-180. KIT Scientific Publishing, (2010)Dolmen: FPGA Swarm for Safety and Liveness Verification., , and . DATE, page 1425-1430. IEEE, (2022)JIT Compiler Security through Low-Cost RISC-V Extension., , and . IPDPS Workshops, page 125-128. IEEE, (2023)Prototyping FPGA through overlays., , and . RSP, page 15-21. IEEE, (2021)Model-driven physical-design automation for FPGAs: fast prototyping and legacy reuse., and . Softw. Pract. Exp., 44 (4): 455-482 (2014)Multilevel Simulation of Heterogeneous Reconfigurable Platforms., and . Int. J. Reconfigurable Comput., (2009)Synthèse portable pour micro-architectures à grain fin. Application aux turbo décodeurs et nanofabriques., , , , , , and . Technique et Science Informatiques, 25 (7): 893-920 (2006)