( en | de | ru )

 

Disambiguation of "Zhu, Jianwen"

Author of the publication

copydeleteadd this publication to your clipboard
Towards automated ECOs in FPGAs.

, , , and . FPGA, page 3-12. ACM, (2009)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Jianwen Zhou

Jianwen She

Jianwen Liu

Junjiang Zhu

Yongming Zhu

 

Other publications of authors with the same name

A Sufficient Condition for Deadlock-Free Adaptive Routing in Mesh Networks., , and . IEEE Comput. Archit. Lett., 14 (2): 111-114 (2015)Towards scalable flow and context sensitive pointer analysis.. DAC, page 831-836. ACM, (2005)A bursty multi-port memory controller with quality-of-service guarantees., and . CODES+ISSS, page 21-28. ACM, (2011)Calligrapher: a new layout-migration engine for hard intellectual property libraries., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (9): 1347-1361 (2005)VariPipe: Low-overhead variable-clock synchronous pipelines., , and . ICCD, page 117-124. IEEE Computer Society, (2009)Timing-Driven Routing of High Fanout Nets., , and . FPL, page 423-428. IEEE Computer Society, (2011)Parallelizing Simulated Annealing-Based Placement Using GPGPU., , and . FPL, page 31-34. IEEE Computer Society, (2010)Calligrapher: A New Layout Migration Engine Based on Geometric Closeness., and . ISQED, page 25-30. IEEE Computer Society, (2004)Performance Efficiency of Context-Flow System-on-Chip Platform., and . ICCAD, page 356-362. IEEE Computer Society / ACM, (2003)A fast Bayesian algorithmic enhancement for real time bit error ratio test (BERT)., and . GlobalSIP, page 1310-1314. IEEE, (2017)