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Tolerating First Level Memory Access Latency in High-Performance Systems., , and . ICPP (1), page 36-43. CRC Press, (1992)The Effect of Compiler Optimizations on Available Parallelism in Scalar Programs., , , , and . ICPP (2), page 142-145. CRC Press, (1991)StageNet: A Reconfigurable Fabric for Constructing Dependable CMPs., , , and . IEEE Trans. Computers, 60 (1): 5-19 (2011)Increasing hardware efficiency with multifunction loop accelerators., , , and . CODES+ISSS, page 276-281. ACM, (2006)Gadara: Dynamic Deadlock Avoidance for Multithreaded Programs., , , , and . OSDI, page 281-294. USENIX Association, (2008)Low-cost prediction-based fault protection strategy., , , and . CGO, page 30-42. ACM, (2020)Multi-objective Exploration for Practical Optimization Decisions in Binary Translation., , , , and . ACM Trans. Embed. Comput. Syst., 18 (5s): 57:1-57:19 (2019)Scratch That (But Cache This): A Hybrid Register Cache/Scratchpad for GPUs., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (11): 2779-2789 (2018)Uncovering hidden loop level parallelism in sequential applications., , , and . HPCA, page 290-301. IEEE Computer Society, (2008)Sentinel Scheduling for VLIW and Superscalar Processors., , , , , , and . ACM Trans. Comput. Syst., 11 (4): 376-408 (1993)preliminary version: ASPLOS 1992: 238-247.