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Disambiguation of "Tomishima, Shigeki"

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Enabling Homomorphically Encrypted Inference for Large DNN Models.

, , , , , , , and . CoRR, (2021)

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Shigeki Nagai

Shigeki Tomo

 

Other publications of authors with the same name

An experimental 256-Mb DRAM with boosted sense-ground scheme., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 29 (11): 1303-1309 (November 1994)A 1 Gb 2 GHz 128 GB/s Bandwidth Embedded DRAM in 22 nm Tri-Gate CMOS Technology., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 50 (1): 150-157 (2015)A 1.0-V 230-MHz column access embedded DRAM for portable MPEG applications., , , , , , , , , and 9 other author(s). IEEE J. Solid State Circuits, 36 (11): 1728-1737 (2001)13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology., , , , , , , , , and 2 other author(s). ISSCC, page 230-231. IEEE, (2014)Enabling Homomorphically Encrypted Inference for Large DNN Models., , , , , , , and . CoRR, (2021)23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache., , , , , , , , , and 10 other author(s). ISSCC, page 404-405. IEEE, (2017)A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs., , , , , and . IEEE J. Solid State Circuits, 29 (4): 432-440 (April 1994)A 5.3-GB/s embedded SDRAM core with slight-boost scheme., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 34 (5): 661-669 (1999)A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs., , , , , , , , , and 11 other author(s). VLSIC, page 186-. IEEE, (2015)0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability., , , , , , , , , and 9 other author(s). IEEE J. Solid State Circuits, 37 (7): 932-940 (2002)