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A 2-Layer Transistor Pixel Stacked CMOS Image Sensor with Oxide-Based Full Trench Isolation for Large Full Well Capacity and High Quantum Efficiency.

K. Zaitsu, A. Matsumoto, M. Nishida, Y. Tanaka, H. Yamashita, Y. Satake, T. Watanabe, K. Araki, N. Nei, K. Nakazawa, J. Yamamoto, M. Uehara, H. Kawashima, Y. Kobayashi, T. Hirano, and K. Tatani. VLSI Technology and Circuits, page 286-287. IEEE, (2022)

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Akira Hayashima

Dairi Matsumoto

Koichi Matsumoto

Teijiro Matsumoto

Tokumyo Matsumoto

Other publications of authors with the same name

Evaluation of MRB Garbage Collection on Parallel Logic Programming Architectures.K. Nishida, Y. Kimura, A. Matsumoto, and A. Goto. ICLP, page 83-95. MIT Press, (1990)KL1 Execution Model for PIM Cluster with Shared Memory.M. Sato, H. Shimizu, A. Matsumoto, K. Rokusawa, and A. Goto. ICLP, page 338-355. MIT Press, (1987)Imperceptible AR Markers for Near-Screen Mobile Interaction.A. Matsumoto, S. Abe, T. Hiraki, S. Fukushima, and T. Naemura. IEEE Access, (2019)Toward a Continuous Intravascular Glucose Monitoring System.B. Beier, K. Musick, A. Matsumoto, A. Panitch, E. Nauman, and P. Irazoqui. Sensors, 11 (1): 409-424 (2011)A 22-ng/ $\surd$ Hz 17-mW Capacitive MEMS Accelerometer With Electrically Separated Mass Structure and Digital Noise- Reduction Techniques.Y. Furubayashi, T. Oshima, T. Yamawaki, K. Watanabe, K. Mori, N. Mori, A. Matsumoto, Y. Kamada, A. Isobe, and T. Sekiguchi. IEEE J. Solid State Circuits, 55 (9): 2539-2552 (2020)Overview of the Parallel Inference Machine Architecture (PIM).A. Goto, M. Sato, K. Nakajima, K. Taki, and A. Matsumoto. FGCS, page 208-229. OHMSHA Ltd. Tokyo and Springer-Verlag, (1988)Design and Performance of a Coherent Cache for Parallel Logic Programming Architectures.A. Goto, A. Matsumoto, and E. Tick. ISCA, page 25-33. ACM, (1989)Architecture and Evaluation of a Reduction-Based Parallel Inference Machine: PIM-R.R. Onai, H. Shimizu, K. Masuda, A. Matsumoto, and M. Aso. LP, volume 221 of Lecture Notes in Computer Science, page 1-12. Springer, (1985)Locally Parallel Cache Design Based on KL1 Memory Access Characteristics.A. Matsumoto. New Generation Comput., 9 (2): 149-170 (1991)Malfunction Issue of SiC-SIT Based DC Circuit Breaker in 400 V DC Power Distribution Systems for Data Centers.S. Abe, S. Yang, M. Shoyama, T. Ninomiya, A. Matsumoto, and A. Fukui. IEICE Trans. Commun., 95-B (6): 1990-1996 (2012)

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Disambiguation of "Matsumoto, Akira"

Please choose a person to relate this publication to

Akira Hayashima

Dairi Matsumoto

Koichi Matsumoto

Teijiro Matsumoto

Tokumyo Matsumoto

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Matsumoto, Akira"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 2-Layer Transistor Pixel Stacked CMOS Image Sensor with Oxide-Based Full Trench Isolation for Large Full Well Capacity and High Quantum Efficiency.

Please choose a person to relate this publication to

Akira Hayashima

Dairi Matsumoto

Koichi Matsumoto

Teijiro Matsumoto

Tokumyo Matsumoto

Other publications of authors with the same name

Disambiguation