Author of the publication

Programmable logic IP cores in SoC design: opportunities and challenges.

, and . CICC, page 63-66. IEEE, (2001)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

An embedded flexible content-addressable memory core for inclusion in a Field-Programmable Gate Array., , and . ISCAS (2), page 885-888. IEEE, (2004)On-chip FPGA Debug Instrumentation for Machine Learning Applications., , , , and . FPGA, page 110-115. ACM, (2019)Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays., , , and . FPT, page 33-40. IEEE, (2004)Concurrently optimizing FPGA architecture parameters and transistor sizing: Implications for FPGA design., , , and . FPT, page 54-61. IEEE Computer Society, (2009)Placement and routing for FPGA architectures supporting wide shallow memories., and . FPT, page 154-161. IEEE, (2003)Enhanced source-level instrumentation for FPGA in-system debug of High-Level Synthesis designs., and . FPT, page 109-116. IEEE, (2016)Sequential synthesizable embedded programmable logic cores for system-on-chip., and . CICC, page 435-438. IEEE, (2004)An Overlay for Rapid FPGA Debug of Machine Learning Applications., , , , , and . FPT, page 135-143. IEEE, (2019)System-on-Chip: Reuse and Integration., , , , , , , , and . Proc. IEEE, 94 (6): 1050-1069 (2006)An analytical model relating FPGA architecture and place and route runtime., and . FPL, page 146-153. IEEE, (2009)