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Application of Cell-Aware Test on an Advanced 3nm CMOS Technology Library., , , , , , , , and . ITC, page 1-6. IEEE, (2019)Formal Methods for Networks on Chips.. ACSD, page 188-189. IEEE Computer Society, (2005)Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip., , and . DATE, page 954-959. EDA Consortium, San Jose, CA, USA, (2007)A Performance Analysis Framework for Real-Time Systems Sharing Multiple Resources., , , and . DATE, page 326-329. IEEE, (2020)Resource utilization and Quality-of-Control trade-off for a composable platform., , , , and . DATE, page 654-659. IEEE, (2016)Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip., , and . CODES+ISSS, page 149-154. ACM, (2007)Modeling reconfiguration in a FPGA with a hardwired network on chip., and . IPDPS, page 1-8. IEEE, (2009)A Unified Programming Model for Time- and Data-Driven Embedded Applications., , and . PDP, page 26-33. IEEE Computer Society, (2018)PUMA: Placement Unification with Mapping and Guaranteed Throughput Allocation on an FPGA Using a Hardwired NoC., and . DSD, page 88-96. IEEE Computer Society, (2011)Composable Dynamic Voltage and Frequency Scaling and Power Management for Dataflow Applications., , , and . DSD, page 107-114. IEEE Computer Society, (2010)