( en | de | ru )

 

Disambiguation of "Kumaki, Takeshi"

Author of the publication

copydeleteadd this publication to your clipboard
Cipher-destroying and secret-key-emitting hardware Trojan against AES core.

, , and . MWSCAS, page 408-411. IEEE, (2013)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Takeshi Morita

Takeshi Morita

Takeshi Imamura

Takeshi Yasui

Takeshi Omori

 

Other publications of authors with the same name

Cipher-destroying and secret-key-emitting hardware Trojan against AES core., , and . MWSCAS, page 408-411. IEEE, (2013)Development of effective information-hiding method for embedded systems., , , , and . MWSCAS, page 1298-1301. IEEE, (2013)Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor., , , , , , , , and . IEICE Trans. Inf. Syst., 90-D (8): 1312-1315 (2007)Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer., , , , , , , , and . IEICE Trans. Inf. Syst., 90-D (1): 334-345 (2007)A flexible multiport content-addressable memory., , and . Syst. Comput. Jpn., 37 (11): 57-67 (2006)Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory., , , , and . IEICE Trans. Inf. Syst., 90-D (1): 346-354 (2007)Development of Compression Tolerable and Highly Implementable Watermarking Method for Mobile Devices., , , , and . IEICE Trans. Inf. Syst., 97-D (3): 593-596 (2014)Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems., , , , and . IEICE Trans. Inf. Syst., 94-D (9): 1742-1754 (2011)Evaluation of advanced pixel-level snakes on cellular hardware platform., , , , , and . NEWCAS, page 1-4. IEEE, (2013)Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine., , , , , , , and . ISCAS, page 525-528. IEEE, (2007)