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A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits., , , , , , , and . VTS, page 197-202. IEEE Computer Society, (2012)On compacting test sets by addition and removal of test vectors., , , and . VTS, page 202-207. IEEE Computer Society, (1994)On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume., , , and . ICCD, page 387-396. IEEE Computer Society, (2003)Hybrid BIST Using Partially Rotational Scan., , , , and . Asian Test Symposium, page 379-384. IEEE Computer Society, (2001)On Improving Defect Coverage of Stuck-at Fault Tests., , , , and . Asian Test Symposium, page 216-223. IEEE Computer Society, (2005)Reduction of NBTI-Induced Degradation on Ring Oscillators in FPGA., , , and . PRDC, page 59-67. IEEE Computer Society, (2014)Aging test strategy and adaptive test scheduling for SoC failure prediction., , , , , and . IOLTS, page 21-26. IEEE Computer Society, (2010)On-Chip Delay Measurement for Degradation Detection And Its Evaluation under Accelerated Life Test., , , , , , and . IOLTS, page 1-6. IEEE, (2020)A Method of Static Test Compaction Based on Don't Care Identification., , and . DELTA, page 392-395. IEEE Computer Society, (2002)On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout., , , , and . ITC, page 83-89. IEEE Computer Society, (2002)