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General switch box modeling and optimization for FPGA routing architectures., , , , and . FPT, page 320-323. IEEE, (2010)Variational capacitance modeling using orthogonal polynomial method., , , , , and . ACM Great Lakes Symposium on VLSI, page 23-28. ACM, (2008)Fault modeling and characteristics of SRAM-based FPGAs (abstract only)., , , , , and . FPGA, page 279. ACM, (2011)A high-performance reconfigurable VLSI architecture for vbsme in H.264., , , , and . IEEE Trans. Consumer Electronics, 54 (3): 1338-1345 (2008)A novel dynamic reconfigurable VLSI architecture for H.264 transforms., , , , and . APCCAS, page 1810-1813. IEEE, (2008)A New Universal Test Pattern Auto-generating Approach for FPGA Logic Resources (abstract only)., and . FPGA, page 263. ACM, (2005)FPART: A Multi-way FPGA Partitioning Procedure Based on the Improved FM Algorithm., , and . ASP-DAC, page 513-518. IEEE, (1998)High-speed and memory-efficient architecture for 2-D 1-Level discrete wavelet transform., , , , and . ICECS, page 486-489. IEEE, (2008)Engineering a scalable Boolean matching based on EDA SaaS 2.0., , , , and . ICCAD, page 750-755. IEEE, (2010)Domain Specific Non-Uniform Routing Architecture for Embedded Programmable IP Core (abstract only)., , and . FPGA, page 269. ACM, (2005)