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V-SAT: A Visual Specification and Analysis Tool for System-On-Chip Exploration.

, , , , , и . EUROMICRO, стр. 1196-1203. IEEE Computer Society, (1999)

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Sebastian Dütting

Som Dutt

Klaus Duttler

Martha Duttle

Johann Duttlinger

 

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Reclocking for high-level synthesis., , и . ASP-DAC, ACM, (1995)Minimization of Memory Traffic in High-Level Synthesis., , и . DAC, стр. 149-154. ACM Press, (1994)Design Reuse: Fact or Fiction? (Panel)., , , , , и . DAC, стр. 562. ACM Press, (1994)Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensions., и . CASES, стр. 104-112. ACM, (2003)Software controlled memory layout reorganization for irregular array access patterns., , , , и . CASES, стр. 179-188. ACM, (2007)HDRL: Homogeneous Dual-Rail Logic for DPA Attack Resistive Secure Circuit Design., и . IEEE Embed. Syst. Lett., 4 (3): 57-60 (2012)VISA synthesis: Variation-aware Instruction Set Architecture synthesis., , и . ASP-DAC, стр. 243-248. IEEE, (2013)Vision-inspired global routing for enhanced performance and reliability., , и . ISQED, стр. 239-244. IEEE, (2013)Minimizing peak power for application chains on architectures with partial dynamic reconfiguration., , , и . FPT, стр. 273-276. IEEE, (2006)Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures., , , и . DAC, стр. 771-776. IEEE, (2007)