( en | de | ru )

 

Disambiguation of "Conzatti, Francesco"

Author of the publication

copydeleteadd this publication to your clipboard
A CT ΔΣ ADC with 9/50MHz BW achieving 73/71dB DR designed for robust blocker tolerance in 14nm FinFET.

, , , , , , , and . ESSCIRC, page 139-142. IEEE, (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Francesco Bettella

Protein secondary structure prediction using optimized scoring functions: a comparative statistical method. FU Berlin, (2009)

Francesco Pinosa

Francesco Solimena

Francesco Bagorda

Francesco Vetere

 

Other publications of authors with the same name

A SAR-assisted Incremental $\Sigma\Delta$ ADC with Accumulation-based S/H Circuit for Shunt Current Measurements., , , , , and . ISCAS, page 1-4. IEEE, (2023)An Intrinsically Linear 13-Level Capacitive DAC for Delta Sigma Modulators., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 70 (4): 1291-1295 (April 2023)A Dual-Mode Second-Order Oversampling Analog-to-Digital Converter., , , and . ESSCIRC, page 215-218. IEEE, (2021)Numerical simulation of advanced CMOS and beyond CMOS devices.. University of Udine, Italy, (2012)A Multi-Subband Monte Carlo study of electron transport in strained SiGe n-type FinFETs., , , , and . ESSDERC, page 322-325. IEEE, (2012)On the Intrinsic Linearity Limitations of Single-Bit Delta Sigma Modulators., , , and . ISCAS, page 1-5. IEEE, (2023)A CT ΔΣ ADC with 9/50MHz BW achieving 73/71dB DR designed for robust blocker tolerance in 14nm FinFET., , , , , , , and . ESSCIRC, page 139-142. IEEE, (2017)Analysis of Operational Amplifier Requirements for Extended-Range Second-Order Incremental ADCs., , , and . ICECS, page 1-4. IEEE, (2020)Thermal Noise Analysis of Accumulation-based S/H Circuit for Shunt Current Sensing., , , , , and . ICECS, page 1-4. IEEE, (2023)A 3.2-MS/s 14-Bit Extended-Range Second-Order Incremental ADC., , , and . ICECS, page 1-4. IEEE, (2021)