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Speeding Up MPSoC virtual platform simulation by Ultra Synchronization Checking Method.

, , , and . DATE, page 353-358. IEEE, (2011)

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ICCAD-2017 CAD contest in resource-aware patch generation., , , and . ICCAD, page 857-862. IEEE, (2017)ICCAD-2015 CAD Contest in Large-scale Equivalence Checking and Function Correction and Benchmark Suite., , , and . ICCAD, page 916-920. IEEE, (2015)ICCAD-2020 CAD Contest in X-value Equivalence Checking and Benchmark Suite : Invited Talk., , , and . ICCAD, page 68:1-68:4. IEEE, (2020)Speeding Up MPSoC virtual platform simulation by Ultra Synchronization Checking Method., , , and . DATE, page 353-358. IEEE, (2011)ICCAD-2014 CAD contest in simultaneous CNF encoder optimization with SAT solver setting selection and benchmark suite., , , and . ICCAD, page 357-360. IEEE, (2014)Interpolation-based incremental ECO synthesis for multi-error logic rectification., , , and . DAC, page 146-151. ACM, (2011)A counterexample-guided interpolant generation algorithm for SAT-based model checking., , , and . DAC, page 118:1-118:6. ACM, (2013)QuteSAT: a robust circuit-based SAT solver for complex circuit structure., , , and . DATE, page 1313-1318. EDA Consortium, San Jose, CA, USA, (2007)2021 CAD Contest Problem A: Functional ECO with Behavioral Change Guidance Invited Paper., , , , , , and . ICCAD, page 1-6. IEEE, (2021)2019 CAD Contest: Logic Regression on High Dimensional Boolean Space., , , , and . ICCAD, page 1-6. ACM, (2019)