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Disambiguation of "Luo, Shien-Chun"

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An ultra-low voltage hearing aid chip using variable-latency design technique.

, , , , , and . ISCAS, page 2543-2546. IEEE, (2014)

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Shimeles Damene Shiene

Junfeng Luo

Jia Luo

Xiaoguang Luo

Yongxiang Luo

 

Other publications of authors with the same name

A Wide-Range Level Shifter Using a Modified Wilson Current Mirror Hybrid Buffer., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (6): 1656-1665 (2014)An ultra-low-power adaptive-body-bias control for subthreshold circuits., , and . VLSI-DAT, page 1-4. IEEE, (2014)Minimum convertible voltage analysis for ratioless and robust subthreshold level conversion., , and . ISCAS, page 2553-2556. IEEE, (2012)MORAS: An energy-scalable system using adaptive voltage scaling., , , , and . VLSI-DAT, page 1-4. IEEE, (2018)An ultra-low voltage hearing aid chip using variable-latency design technique., , , , , and . ISCAS, page 2543-2546. IEEE, (2014)An Adaptive Pulse-Triggered Flip-Flop for a High-Speed and Voltage-Scalable Standard Cell Library., , and . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (10): 677-681 (2013)Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells., , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (12): 947-951 (2014)An Energy-Efficient Dual-Edge Triggered Level-Converting Flip-Flop., and . ISCAS, page 1157-1160. IEEE, (2007)Customization of a Deep Learning Accelerator.. VLSI-DAT, page 1-2. IEEE, (2019)Energy-Efficient Dual-Edge-Triggered Level Converting Flip Flops With Symmetry in Setup Times and Insensitivity to Output Parasitics., and . IEEE Trans. Very Large Scale Integr. Syst., 17 (11): 1659-1663 (2009)