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An overview of the Kyushu University reconfigurable parallel processor., , , and . SIGARCH Comput. Archit. News, 16 (4): 130-137 (1988)Semantic image retrieval for complex queries using a knowledge parser., , , and . Multimedia Tools Appl., 77 (9): 10733-10751 (2018)A Reconfigurable Data-Path Accelerator Based on Single Flux Quantum Circuits., , , , , , , and . IEICE Trans. Electron., 97-C (3): 141-148 (2014)Collective Communication Costs Analysis over Gigabit Ethernet and InfiniBand., , and . HiPC, volume 4297 of Lecture Notes in Computer Science, page 547-559. Springer, (2006)Circuit Area-latency Optimization Technique for High-precision Elementary Functions., , and . APCCAS, page 1406-1409. IEEE, (2006)REDEFIS: a system with a redefinable instruction set processor., , , , , and . SBCCI, page 14-19. ACM, (2006)Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems., , and . Intelligent Memory Systems, volume 2107 of Lecture Notes in Computer Science, page 169-178. Springer, (2000)Way-predicting set-associative cache for high performance and low energy consumption., , and . ISLPED, page 273-275. ACM, (1999)A history-based I-cache for low-energy multimedia applications., , and . ISLPED, page 148-153. ACM, (2002)A Reconfigurable Functional Unit with Conditional Execution for Multi-Exit Custom Instructions., , , and . IEICE Trans. Electron., 91-C (4): 497-508 (2008)