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Estimating data bus size for custom processors in embedded systems., , , and . Des. Autom. Embed. Syst., 10 (1): 5-26 (2005)Toward Multi-Layer Holistic Evaluation of System Designs., , , , , and . IEEE Comput. Archit. Lett., 15 (1): 58-61 (2016)Analyzing Effects of Trace Cache Configurations on the Prediction of Indirect Branches., , and . J. Instr. Level Parallelism, (2006)Unified Assign and Schedule: A New Approach to Scheduling for Clustered Register File Microarchitectures., , and . MICRO, page 308-315. ACM/IEEE Computer Society, (1998)FPGA Implementation of a Lattice Quantum Chromodynamics Algorithm Using Logarithmic Arithmetic., , , , and . IPDPS, IEEE Computer Society, (2005)Eliminating energy of same-content-cell-columns of on-chip SRAM arrays., , , , , and . ISLPED, page 181-186. IEEE/ACM, (2011)VDIBA-Based Current-Mode PID Controller Design., , and . J. Circuits Syst. Comput., 32 (17): 2350288:1-2350288:17 (November 2023)Low-cost Techniques for Reducing Branch Context Pollution in a Soft Realtime Embedded Multithreaded Processor., , and . SBAC-PAD, page 37-44. IEEE Computer Society, (2007)Memory array protection: check on read or check on write?, , , , and . DATE, page 214-219. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Energy-Efficient Simultaneous Thread Fetch from Different Cache Levels in a Soft Real-Time SMT Processor., , , , and . SAMOS, volume 5114 of Lecture Notes in Computer Science, page 12-22. Springer, (2008)