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Disambiguation of "Palumbo, Gaetano"

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Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic.

, , and . PATMOS, volume 5349 of Lecture Notes in Computer Science, page 136-145. Springer, (2008)

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Gaetano Romano

Gaetano Cicinnati

Gaetano Vitale

Gaetano Romano

Raffaele Gaetano

 

Other publications of authors with the same name

The noise performance of CMOS Miller operational transconductance amplifiers with embedded current-buffer frequency compensation., , , and . I. J. Circuit Theory and Applications, 45 (4): 457-465 (2017)Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates., and . PATMOS, volume 1918 of Lecture Notes in Computer Science, page 265-275. Springer, (2000)Flip-Flop Energy/Performance Versus Clock Slope and Impact on the Clock Network Design., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 57-I (6): 1273-1286 (2010)Design Procedures for Three-Stage CMOS OTAs With Nested-Miller Compensation., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 54-I (5): 933-940 (2007)A Simple Circuit Approach to Reduce Delay Variations in Domino Logic Gates., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (10): 2292-2300 (2012)Advances in Reversed Nested Miller Compensation., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 54-I (7): 1459-1470 (2007)Guest Editorial Special Issue on Selected Papers from PRIME 2017 and SMACD 2017., , , , , , , and . Integr., (2018)A Novel 0.6V MCML D-Latch Topology exploiting Dynamic Body Bias Threshold Lowering., , and . ICECS, page 233-236. IEEE, (2018)Comparative analysis of the robustness of master-slave flip-flops against variations., , and . ICECS, page 117-120. IEEE, (2015)Figures of merit for class AB input stages., , and . ECCTD, page 749-752. IEEE, (2011)