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MVDR based adaptive beamformer design and its FPGA implementation for ultrasonic imaging.

, , , , and . APCCAS, page 143-145. IEEE, (2016)

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Low-Voltage and Low-Power True-Single-Phase 16-Transistor Flip-Flop Design., , , , , and . Sensors, 22 (15): 5696 (2022)MVDR based adaptive beamformer design and its FPGA implementation for ultrasonic imaging., , , , and . APCCAS, page 143-145. IEEE, (2016)Projection Matching Pursuit based DoA Estimation Scheme and its FPGA Implementation., , , , and . ISOCC, page 109-110. IEEE, (2019)Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme., , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (2): 361-366 (2012)Low Power Multipliers Using Enhenced Row Bypassing Schemes., , , and . SiPS, page 136-141. IEEE, (2007)Semantic Lung Segmentation Using Convolutional Neural Networks., , , and . Bildverarbeitung für die Medizin, page 75-80. Springer, (2020)Low Power Multiplier Designs Based on Improved Column Bypassing Schemes., , , and . APCCAS, page 594-597. IEEE, (2006)Low power 10-transistor full adder design based on degenerate pass transistor logic., , and . ISCAS, page 496-499. IEEE, (2012)A high speed and energy efficient full adder design using complementary & level restoring carry logic., , , and . ISCAS, IEEE, (2006)A 0.5V True-Single-Phase 16T Flip-Flop in 180-nm CMOS for IoT Applications., , , , and . ICCE-TW, page 1-2. IEEE, (2021)