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Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis., , , , , , , , and . ICCAD, page 458-465. IEEE, (2013)SEAS: a system for early analysis of SoCs., , , , , , , and . CODES+ISSS, page 150-155. ACM, (2003)Hierarchical constraint transformation based on genetic optimization for analog system synthesis., , , and . Integr., 39 (3): 267-290 (2006)A genetic approach to simultaneous parameter space exploration and constraint transformation in analog synthesis., , and . ISCAS (6), page 362-365. IEEE, (1999)A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications., , , and . ACM Trans. Design Autom. Electr. Syst., 9 (2): 238-271 (2004)Architecting voltage islands in core-based system-on-a-chip designs., , , and . ISLPED, page 180-185. ACM, (2004)Design topology aware physical metrics for placement analysis., and . ACM Great Lakes Symposium on VLSI, page 186-191. ACM, (2003)Temperature-Aware Voltage Islands Architecting in System-on-Chip Design., , , , , and . ICCD, page 689-696. IEEE Computer Society, (2005)Energy Efficiency Boost in the AI-Infused POWER10 Processor., , , , , , , , , and 16 other author(s). ISCA, page 29-42. IEEE, (2021)A power estimation methodology for systemC transaction level models., , and . CODES+ISSS, page 142-147. ACM, (2005)