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A Novel Application-specific Instruction-set Processor Design Approach for Video Processing Acceleration., , , and . VLSI Signal Processing, 47 (3): 297-315 (2007)Vt-conscious repeater insertion in power-managed VLSI., , and . ISIC, page 99-102. IEEE, (2014)Joint power control and beamformer design with antenna selection., , and . CCECE, page 1-4. IEEE, (2017)An interface for the I2C protocol in the WaferBoard™., , and . ISCAS, page 1492-1495. IEEE, (2013)Spurs modeling in direct digital period synthesizers related to phase accumulator truncation., , and . ISCAS (3), page 389-392. IEEE, (2004)Design and validation of a novel reconfigurable and defect tolerant JTAG scan chain., , , and . ISCAS, page 2559-2562. IEEE, (2014)High-voltage operational amplifier based on dual floating-gate transistors., , , and . ISCAS, IEEE, (2006)Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector., and . ISCAS (4), page 369-372. IEEE, (2004)Fast parameters optimization of an iterative decoder using a configurable hardware accelerator., , , , , and . ISCAS (4), page 4159-4162. IEEE, (2005)An FPGA Overlay Architecture for Cost Effective Regular Expression Search (Abstract Only)., , and . FPGA, page 287-288. ACM, (2017)