( en | de | ru )

 

Disambiguation of "Roy, Kaushik"

Author of the publication

copydeleteadd this publication to your clipboard
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies.

, , , , and . DATE, page 926-931. IEEE Computer Society, (2005)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Kaushik Bhaganagarapu

Kaushik Biswas

Kaushik Ravichandran

Kaushik Mitra

Rahul Kaushik

 

Other publications of authors with the same name

Relevant-features based Auxiliary Cells for Energy Efficient Detection of Natural Errors., , and . CoRR, (2020)A novel approach to high-level switching activity modeling with applications to low-power DSP system synthesis., , , and . IEEE Trans. Signal Process., 49 (12): 3157-3167 (2001)Complexity reduction of digital filters using shift inclusive differential coefficients., , and . IEEE Trans. Signal Process., 52 (6): 1760-1772 (2004)Explicitly Trained Spiking Sparsity in Spiking Neural Networks with Backpropagation., , , and . CoRR, (2020)LVDCSL: a high fan-in, high-performance, low-voltage differential current switch logic family., and . IEEE Trans. Very Large Scale Integr. Syst., 6 (4): 573-577 (1998)Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ., , , and . IEEE Trans. Very Large Scale Integr. Syst., 11 (5): 863-870 (2003)Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design., and . IEEE Trans. Very Large Scale Integr. Syst., 20 (2): 319-332 (2012)A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations., , , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (3): 349-357 (2005)Accurate power estimation of CMOS sequential circuits., and . IEEE Trans. Very Large Scale Integr. Syst., 4 (3): 369-380 (1996)A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array., , , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (9): 1727-1730 (2011)