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Disambiguation of "Jokar, Ehsan"

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Hardware-Algorithm Co-Design of a Compressed Fuzzy Active Learning Method.

, , , , , and . IEEE Trans. Circuits Syst., 67-I (12): 4932-4945 (2020)

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Susan Ehsani-Yeganeh

Ehsan Khaljani

Ehsan Noruzifar

Ehsan Ardestanizadeh

Sirous Ehsani

 

Other publications of authors with the same name

An Efficient Uniform-Segmented Neuron Model for Large-Scale Neuromorphic Circuit Design: Simulation and FPGA Synthesis Results., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (6): 2336-2349 (2019)GWBM: an algorithm based on grey wolf optimization and balanced modularity for community discovery in social networks., , and . J. Supercomput., 78 (5): 7354-7377 (2022)Overlapping community detection in complex networks using fuzzy theory, balanced link density, and label propagation., , and . Expert Syst. J. Knowl. Eng., (2022)Systematic Computation of Nonlinear Bilateral Dynamical Systems With a Novel Low-Power Log-Domain Circuit., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (8): 2013-2025 (2017)Discovering community structure in social networks based on the synergy of label propagation and simulated annealing., , and . Multim. Tools Appl., 81 (15): 21449-21470 (2022)A Novel Nonlinear Function Evaluation Approach for Efficient FPGA Mapping of Neuron and Synaptic Plasticity Models., , and . IEEE Trans. Biomed. Circuits Syst., 13 (2): 454-469 (2019)Hardware-Algorithm Co-Design of a Compressed Fuzzy Active Learning Method., , , , , and . IEEE Trans. Circuits Syst., 67-I (12): 4932-4945 (2020)Digital Multiplierless Realization of a Calcium-Based Plasticity Model., and . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (7): 832-836 (2017)