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Clock Network Synthesis with Concurrent Gate Insertion., , and . PATMOS, volume 6448 of Lecture Notes in Computer Science, page 228-237. Springer, (2010)A robust approach for process variation aware mask optimization., , and . DATE, page 1591-1594. ACM, (2015)ISPD 2019 Initial Detailed Routing Contest and Benchmark with Advanced Routing Rules., , , , , and . ISPD, page 147-151. ACM, (2019)ISPD 2018 Initial Detailed Routing Contest and Benchmarks., , , , and . ISPD, page 140-143. ACM, (2018)Timing driven routing tree construction., , and . SLIP, page 1-8. IEEE Computer Society, (2017)Fence-aware detailed-routability driven placement., , , and . SLIP, page 1-7. IEEE Computer Society, (2017)Triple Patterning Lithography Aware Optimization and Detailed Placement Algorithms for Standard Cell-Based Designs., , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (4): 1319-1332 (2016)Routability-driven and fence-aware legalization for mixed-cell-height circuits., , , , and . DAC, page 150:1-150:6. ACM, (2018)Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees., , , , , , and . ISPD, page 10-17. ACM, (2018)RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs., , , , , , , , and . ICCAD, page 67. ACM, (2016)