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Disambiguation of "Rajski, Janusz"

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Testing of Glue Logic Interconnects Using Boundary Scan Architecture.

, , , and . ITC, page 700-711. IEEE Computer Society, (1989)

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Janusz Panzer

Janusz Rat

Janusz Gatniejewski

Janusz Surzykiewicz

Janusz Bogdanowicz

 

Other publications of authors with the same name

High Performance Dense Ring Generators., , , and . IEEE Trans. Computers, 55 (1): 83-87 (2006)Embedded deterministic test points for compact cell-aware tests., , , , , , , , , and . ITC, page 1-8. IEEE, (2015)Self-test methodology for at-speed test of crosstalk in chip interconnects., , and . DAC, page 619-624. ACM, (2000)On Linear Dependencies in Subspaces of LFSR-Generated Sequences., and . IEEE Trans. Computers, 45 (10): 1212-1216 (1996)Built-In Self-Test for Systems on Silicon., , and . VLSI Design, page 609-610. IEEE Computer Society, (1999)H2B: Crypto Hash Functions Based on Hybrid Ring Generators., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (2): 442-455 (February 2024)Star-EDT: Deterministic On-Chip Scheme Using Compressed Test Patterns., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (4): 683-693 (2017)Cube-Contained Random Patterns and Their Applications to the Complete Testing of Synthesized Multi-Level Circuits., and . ITC, page 473-482. IEEE Computer Society, (1991)On Using Implied Values in EDT-based Test Compression., , , , and . DAC, page 11:1-11:6. ACM, (2014)Embedded deterministic test., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (5): 776-792 (2004)