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Is IDDQ testing not applicable for deep submicron VLSI in year 2011?

, , , and . Asian Test Symposium, page 338-343. IEEE Computer Society, (2000)

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A 0.2-0.6 V ring oscillator design using bootstrap technique., , and . A-SSCC, page 333-336. IEEE, (2011)A sub-100µW multi-functional cardiac signal processor for mobile healthcare applications., , , , , , , , , and 4 other author(s). VLSIC, page 156-157. IEEE, (2012)A Near-Threshold 480 MHz 78 µW All-Digital PLL With a Bootstrapped DCO., , , and . IEEE J. Solid State Circuits, 48 (11): 2805-2814 (2013)Design of a Subthreshold-Supply Bootstrapped CMOS Inverter Based on an Active Leakage-Current Reduction Technique., , and . IEEE Trans. Circuits Syst. II Express Briefs, 59-II (1): 55-59 (2012)ECCSyn: a Synthesis Tool for ECC Circuits., and . ISCAS, page 1706-1709. IEEE, (1993)A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus., , , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (2): 306-311 (2009)Finite State Machine Synthesis for At-Speed Oscillation Testability., , , , and . Asian Test Symposium, page 360-365. IEEE Computer Society, (2005)All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses., , , , and . DATE, page 527-531. IEEE Computer Society / ACM, (2000)Multilevel full-chip routing with testability and yield enhancement., , , , and . SLIP, page 29-36. ACM, (2005)A low-power analog-to-digital converter with digitalized amplifier for PAM systems., , and . MWSCAS, page 109-112. IEEE, (2014)