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CATAPULT: Concurrent Automatic Testing Allowing Parallelization and Using Limited Topology.

, , , and . DAC, page 597-600. ACM, (1988)

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Heuristics to Compute Variable Orderings for Efficient Manipulation of Ordered Binary Decision Diagrams., , , and . DAC, page 417-420. ACM, (1991)Linear finite state machine for lD ILAs., , , and . VTS, page 325-332. IEEE Computer Society, (1994)Exact ordered binary decision diagram size when representing classes of symmetric functions., , and . J. Electron. Test., 2 (3): 243-259 (1991)CATAPULT: Concurrent Automatic Testing Allowing Parallelization and Using Limited Topology., , , and . DAC, page 597-600. ACM, (1988)An Accurate Delay Model for BiCMOS Gates and Off-chip Drivers., , , and . ISCAS, page 1539-1542. IEEE, (1993)Efficient variable ordering and partial representation algorithm., , , , , and . VLSI Design, page 81-86. IEEE Computer Society, (1995)The roles of controllability and observability in design for test., , , and . VTS, page 211-216. IEEE Computer Society, (1992)Conversion of small functional test sets of nonscan blocks to scan patterns., , and . ITC, page 691-700. IEEE Computer Society, (2000)LFSR based deterministic hardware for at-speed BIST., , , and . VTS, page 201-207. IEEE Computer Society, (1993)Functional Approaches to Generating Orderings for Efficient Symbolic Representations., , and . DAC, page 624-627. IEEE Computer Society Press, (1992)