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SINET5: A low-latency and high-bandwidth backbone network for SDN/NFV Era., , , , , , , , , and 1 other author(s). ICC, page 1-7. IEEE, (2017)A link removal methodology for Networks-on-Chip on reconfigurable systems., , , and . FPL, page 269-274. IEEE, (2008)AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation., , , , and . NOCS, page 6:1-6:8. IEEE, (2018)The Impact of Application Mapping on Non-Random and Random Network Topologies., and . ISPA/BDCloud/SocialCom/SustainCom, page 16-25. IEEE, (2019)Designing High-Performance Interconnection Networks with Host-Switch Graphs., , , , and . IEEE Trans. Parallel Distributed Syst., 30 (2): 315-330 (2019)A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks., , and . PDCS, page 24-31. ISCA, (2006)Scalable Low-Latency Inter-FPGA Networks., , , , and . IPDPS, page 234-245. IEEE, (2022)Message from the Organizers: CANDAR 2022., , , and . CANDAR, page viii. IEEE, (2022)Efficient Scheduling Algorithms on Bandwidth Reservation Service of Internet Using Metaheuristics., , , , , and . ISDA, page 683-688. IEEE Computer Society, (2009)3D Layout of Spidergon, Flattened Butterfly and Dragonfly on a Chip Stack with Inductive Coupling Through Chip Interface., , , , and . ISPAN-FCST-ISCC, page 52-59. IEEE Computer Society, (2017)