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Towards verified programming of embedded devices.

, , , , и . DATE, стр. 1445-1450. IEEE, (2019)

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Jean Pierre Vité

Jean-Pierre Cahen

Jean-Pierre Ruiz

Jean Pierre Bünter

Jean-Pierre Mittaz

 

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A higher-order extension for imperative synchronous languages., , и . SCOPES, стр. 7. ACM, (2010)Parallel Composition and Modular Verification of Computer Controlled Systems in Differential Dynamic Logic., , , и . FM, том 11800 из Lecture Notes in Computer Science, стр. 354-370. Springer, (2019)Automated Generation of Synchronous Formal Models from SystemC Descriptions., , и . Journal of Circuits, Systems, and Computers, 28 (4): 1950061:1-1950061:21 (2019)An algebraic theory for behavioral modeling and protocol synthesis in system design., и . Formal Methods Syst. Des., 28 (2): 131-151 (2006)A Compositional Behavioral Modeling Framework for Embedded System Design and Conformance Checking., , , и . Int. J. Parallel Program., 33 (6): 613-643 (2005)POLYCHRONY for System Design., , и . Journal of Circuits, Systems, and Computers, 12 (3): 261-304 (2003)Formal Verification of Solidity contracts in Event-B., , , , и . CoRR, (2020)Formal Modeling and Verification of Blockchain System., , , , , и . ICCMS, стр. 231-235. ACM, (2018)Generating Multi-Threaded code from Polychronous Specifications., , , и . SLAP@ETAPS, том 238 из Electronic Notes in Theoretical Computer Science, стр. 57-69. Elsevier, (2008)A Functional Programming Framework for Latency Insensitive Protocol Validation., , , , и . FMGALS@MEMOCODE, том 146 из Electronic Notes in Theoretical Computer Science, стр. 169-188. Elsevier, (2005)