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Disambiguation of "Nandwana, Romesh Kumar"

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A 0.0021 mm2 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS.

, , , , , and . IEEE J. Solid State Circuits, 52 (1): 8-20 (2017)

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Romesh Sharma

Romesh Chandra Sen

Rohini Kumar

Pardeep Kumar

Aditya Kumar

 

Other publications of authors with the same name

A Process and Temperature Insensitive CMOS Linear TIA for 100 Gb/s/λ PAM-4 Optical Links., , , , , , and . IEEE J. Solid State Circuits, 54 (11): 3180-3190 (2019)12.2 A1.8V 30-to-70MHz 87% peak-efficiency 0.32mm2 4-phase time-based buck converter consuming 3μA/MHz quiescent current in 65nm CMOS., , , , and . ISSCC, page 1-3. IEEE, (2015)8.6 A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS., , , , and . ISSCC, page 152-153. IEEE, (2017)A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider., , , , and . IEEE J. Solid State Circuits, 51 (8): 1771-1784 (2016)Clock multiplication techniques for high-speed I/Os. University of Illinois Urbana-Champaign, USA, (2017)A 7 pA/$\surdHz$ Asymmetric Differential TIA for 100Gb/s PAM-4 links with -14dBm Optical Sensitivity in 16nm CMOS., , , , , , and . ISSCC, page 206-207. IEEE, (2023)23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS., , , , , , , , , and . ISSCC, page 398-399. IEEE, (2016)A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS., , , , , , , , and . VLSIC, page 352-. IEEE, (2015)A 0.7V time-based inductor for fully integrated low bandwidth filter applications., , , , , , and . CICC, page 1-4. IEEE, (2017)A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter., , , , and . CICC, page 1-4. IEEE, (2015)