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Disambiguation of "Soens, Charlotte"

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A 60GHz 8-way phased array front-end with TR switching and calibration-free beamsteering in 28nm CMOS.

, , , , , , and . ESSCIRC, page 203-206. IEEE, (2017)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Sabine Soens

Charlotte Möser

Essays on monetary policy: a Bayesian approach. HU Berlin, (2009)

Charlotte Girod

Charlotte Dahn

Charlotte Dege

 

Other publications of authors with the same name

Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies., , , , , , , , , and 5 other author(s). ISSCC, page 528-529. IEEE, (2008)Low-Area Active-Feedback Low-Noise Amplifier Design in Scaled Digital CMOS., , , , and . IEEE J. Solid State Circuits, 43 (11): 2422-2433 (2008)A CMOS 100 MHz to 6 GHz software defined radio analog front-end with integrated pre-power amplifier., , , , , , , , and . ESSCIRC, page 436-439. IEEE, (2007)A 60-GHz 8-Way Phased-Array Front-End With T/R Switching and Calibration-Free Beamsteering in 28-nm CMOS., , , , , , , and . IEEE J. Solid State Circuits, 53 (7): 2001-2011 (2018)A low-power radio chipset in 40nm LP CMOS with beamforming for 60GHz high-data-rate wireless communication., , , , , , , , , and 4 other author(s). ISSCC, page 236-237. IEEE, (2013)Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance., , , and . DATE, page 270-275. IEEE Computer Society, (2005)Interactive presentation: Simulation methodology and experimental verification for the analysis of substrate noise on LC-VCO's., , , , and . DATE, page 1520-1525. EDA Consortium, San Jose, CA, USA, (2007)A 60GHz 8-way phased array front-end with TR switching and calibration-free beamsteering in 28nm CMOS., , , , , , and . ESSCIRC, page 203-206. IEEE, (2017)A low-power 57-to-66GHz transceiver in 40nm LP CMOS with -17dB EVM at 7Gb/s., , , , , , , , , and 2 other author(s). ISSCC, page 268-270. IEEE, (2012)Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance, , , and . CoRR, (2007)