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Disambiguation of "Devadas, Srinivas"

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AEGIS: A single-chip secure processor.

, , and . Inf. Secur. Tech. Rep., 10 (2): 63-73 (2005)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Vinay Devadas

Deepika Devadas

Srinivas Jagarlamudi

Srinivas Yarlanki

Girish Srinivas

 

Other publications of authors with the same name

Topological Optimization of Multiple-Level Array Logic., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 6 (6): 915-941 (1987)Verification of relations between synchronous machines., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 12 (12): 1947-1959 (1993)A unified approach to the synthesis of fully testable sequential machines., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (1): 39-50 (1991)Irredundant sequential machines via optimal logic synthesis., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 9 (1): 8-18 (1990)Addendum to "Synthesis of robust delay-fault testable circuits: Theory"., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (4): 445-446 (1996)Code density optimization for embedded DSP processors using data compression techniques., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 17 (7): 601-608 (1998)Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures., , and . Des. Autom. Embed. Syst., 4 (1): 5-22 (1999)Logic verification algorithms and their parallel implementation., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 8 (2): 181-189 (1989)Proof of Space from Stacked Expanders., and . TCC (B1), volume 9985 of Lecture Notes in Computer Science, page 262-285. (2016)Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks., , and . ITC, page 887-896. IEEE Computer Society, (1991)