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Disambiguation of "Ho, Nam"

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Modeling methodology for multi-die chip design based on gem5/SystemC co-simulation.

, , , , , , , and . RAPIDO@HiPEAC, page 35-41. ACM, (2024)

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Nam Ho

Jin Nam

Beomseok Nam

Alexander Nam

Veronika Maria Namyslo

 

Other publications of authors with the same name

COMPESCE: A Co-design Approach for Memory Subsystem Performance Analysis in HPC Many-Cores., , , , , , , , , and 1 other author(s). ARCS, volume 13949 of Lecture Notes in Computer Science, page 105-119. Springer, (2023)Optimization of Application-Specific L1 Cache Translation Functions of the LEON3 Processor., , and . SoCPaR, volume 1182 of Advances in Intelligent Systems and Computing, page 266-276. Springer, (2019)Multilevel simulation-based co-design of next generation HPC microprocessors., , , , , , , , , and 10 other author(s). PMBS, page 18-29. IEEE, (2021)Mont-Blanc 2020: Towards Scalable and Power Efficient European HPC Processors., , , , , , , , , and 5 other author(s). DATE, page 136-141. IEEE, (2021)Modeling methodology for multi-die chip design based on gem5/SystemC co-simulation., , , , , , , and . RAPIDO@HiPEAC, page 35-41. ACM, (2024)Evolution of application-specific cache mappings., , and . Int. J. Hybrid Intell. Syst., 16 (3): 149-161 (2020)Development of a simulation method for the subsea production system., , and . J. Comput. Des. Eng., 1 (3): 173-186 (2014)Fall-Detection Algorithm Using 3-Axis Acceleration: Combination with Simple Threshold and Hidden Markov Model., , , , and . J. Appl. Math., (2014)Reflector Attack Traceback System with Pushback Based iTrace Mechanism., , , , , and . ICICS, volume 3269 of Lecture Notes in Computer Science, page 236-248. Springer, (2004)CMB-S4 Science Book, First Edition, , , , , , , , , and 76 other author(s). (2016)cite arxiv:1610.02743.