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Efficient techniques for canceling transceiver noise., , , , and . VLSI-DAT, page 1-4. IEEE, (2013)Digitally-assisted analog circuits for a 10 Gbps, 395 fJ/b optical receiver in 40 nm CMOS., , , , , , , , , and 2 other author(s). A-SSCC, page 29-32. IEEE, (2011)Modeling and Design of High-Radix On-Chip Crossbar Switches., , , and . NOCS, page 20:1-20:8. ACM, (2015)Guest Editorial for Special Issue on High-Performance Multichip Interconnections., , and . IEEE Trans. Circuits Syst. II Express Briefs, 57-II (5): 317-318 (2010)High-performance ULSI: the real limiter to interconnect scaling.. SLIP, page 3. ACM, (2005)The future of wires., , and . Proc. IEEE, 89 (4): 490-504 (2001)Research Challenges for On-Chip Interconnection Networks., , , , , and . IEEE Micro, 27 (5): 96-108 (2007)3.3 A 14nm 1GHz FPGA with 2.5D transceiver integration., , , , , , , , , and 8 other author(s). ISSCC, page 54-55. IEEE, (2017)High-Speed and Low-Energy Capacitively-Driven On-Chip Wires., , , , , , and . ISSCC, page 412-612. IEEE, (2007)Long Wires and Asynchronous Control., , and . ASYNC, page 240-249. IEEE Computer Society, (2004)