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Leakage power reduction using stress-enhanced layouts., , , , and . DAC, page 912-917. ACM, (2008)Design-patterning co-optimization of SRAM robustness for double patterning lithography., , and . ASP-DAC, page 713-718. IEEE, (2012)Statistical modeling of cross-coupling effects in VLSI interconnects., , , and . ASP-DAC, page 503-506. ACM Press, (2005)A library compatible driver output model for on-chip RLC transmission lines., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (1): 128-136 (2004)Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization., , , , , and . ISQED, page 284-290. IEEE Computer Society, (2005)REBEL and TDC: Two embedded test structures for on-chip measurements of within-die path delay variations., , , , and . ICCAD, page 170-177. IEEE Computer Society, (2011)Active learning framework for post-silicon variation extraction and test cost reduction., , , and . ICCAD, page 508-515. IEEE, (2010)Frequency domain decomposition of layouts for double dipole lithography.. DAC, page 404-407. ACM, (2010)TSV/FET proximity study using dense addressable transistor arrays., , , and . IRPS, page 3. IEEE, (2015)Characterization and design for variability and reliability., , and . CICC, page 341-346. IEEE, (2008)