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Disambiguation of "Saluja, Kewal K."

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Diagnosis of Delay Faults Considering Hazards.

, , , , and . ISVLSI, page 503-508. IEEE Computer Society, (2015)

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Heinz Kewald

Kewal Krishen Mehta

Aman K K Bhasin

K Schweizerhof

K Schaber

 

Other publications of authors with the same name

A Novel Approach for Testing Memories Using a Built-In Self Testing Technique., and . ITC, page 830-839. IEEE Computer Society, (1986)SEU tolerant SRAM cell., , , , and . ISQED, page 597-602. IEEE, (2011)Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors., , , and . DATE, page 1572-1577. IEEE Computer Society, (2010)An implementation and analysis of a concurrent built-in self-test technique., and . FTCS, page 164-169. IEEE Computer Society, (1988)Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits., , , , and . ASP-DAC, page 659-664. IEEE, (2006)Optimal Sensor Distribution for Maximum Exposure in A Region with Obstacles., , and . GLOBECOM, IEEE, (2006)Fault Tolerant Lanczos Eigensolver via an Invariant Checking Method., , and . J. Electron. Test., 37 (3): 409-422 (2021)A Study of Capture-Safe Test Generation Flow for At-Speed Testing., , , , , , , , , and 1 other author(s). IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (7): 1309-1318 (2010)A Novel ATPG Method for Capture Power Reduction during Scan Testing., , , , , , and . IEICE Trans. Inf. Syst., 90-D (9): 1398-1405 (2007)Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester., , , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (7): 790-800 (2007)