Author of the publication

A 7-Die 3D Stacked 3840×2160@120 fps Motion Estimation Processor.

, , , , and . IEICE Trans. Electron., 100-C (3): 223-231 (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Transform-based fast mode and depth decision algorithm for HEVC intra prediction., , and . ASICON, page 1-4. IEEE, (2013)Unified VLSI Architecture of Motion Vector and Boundary Strength Parameter Decoder for 8K UHDTV HEVC Decoder., , , , and . PCM, volume 8879 of Lecture Notes in Computer Science, page 74-83. Springer, (2014)A 610 Mbin/s CABAC decoder for H.265/HEVC level 6.1 applications., , , and . ICIP, page 1268-1272. IEEE, (2014)A high-performance CABAC encoder architecture for HEVC and H.264/AVC., , , and . ICIP, page 1568-1572. IEEE, (2013)Embedded Frame Compression for Energy-Efficient Computer Vision Systems., , , and . ISCAS, page 1-5. IEEE, (2018)A fixed-complexity HEVC inter mode filtering algorithm based on distribution of IME-FME cost ratio., , , and . ISCAS, page 617-620. IEEE, (2015)Intra prediction architecture for H.264/AVC QFHD encoder., , , and . PCS, page 450-453. IEEE, (2010)A Frame-Parallel 2 Gpixel/s Video Decoder Chip for UHDTV and 3-DTV/FTV Applications., , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (12): 2768-2781 (2015)An Advanced Hierarchical Motion Estimation Scheme With Lossless Frame Recompression and Early-Level Termination for Beyond High-Definition Video Coding., , , and . IEEE Trans. Multim., 14 (2): 237-249 (2012)High-Throughput Power-Efficient VLSI Architecture of Fractional Motion Estimation for Ultra-HD HEVC Video Encoding., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (12): 3138-3142 (2015)