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A Low-Cost Floating-Point Dot-Product-Dual-Accumulate Architecture for HPC-Enabled AI.

H. Tan, L. Huang, Z. Zheng, H. Guo, Q. Yang, L. Shen, G. Chen, L. Xiao, and N. Xiao. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (2): 681-693 (February 2024)

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Yang Yang

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On-Chip Memory System Optimization Design for the FT64 Scientific Stream Accelerator.M. Wen, N. Wu, C. Zhang, Q. Yang, J. Ren, Y. He, W. Wu, J. Chai, M. Guan, and C. Xun. IEEE Micro, 28 (4): 51-70 (2008)A Stream System-on-Chip Architecture for High Speed Target Recognition Based on Biologic Vision.N. Wu, Q. Yang, M. Wen, Y. He, C. Xun, and C. Zhang. Asia-Pacific Computer Systems Architecture Conference, volume 4697 of Lecture Notes in Computer Science, page 256-267. Springer, (2007)Unified Virtual Memory Support for Deep CNN Accelerator on SoC FPGA.T. Xiao, Y. Qiao, J. Shen, Q. Yang, and M. Wen. ICA3PP (1), volume 9528 of Lecture Notes in Computer Science, page 64-76. Springer, (2015)SAT: A Stream Architecture Template for Embedded Applications.Q. Yang, N. Wu, M. Wen, Y. He, H. Su, and C. Zhang. CIT, page 1711-1718. IEEE Computer Society, (2010)Enabling a Uniform OpenCL Device View for Heterogeneous Platforms.D. Huang, C. Xun, N. Wu, M. Wen, C. Zhang, X. Cai, and Q. Yang. IEICE Trans. Inf. Syst., 98-D (4): 812-823 (2015)Efficient Multiple-Precision and Mixed-Precision Floating-Point Fused Multiply-Accumulate Unit for HPC and AI Applications.H. Tan, R. Yan, L. Yang, L. Huang, L. Xiao, and Q. Yang. ICA3PP, volume 13777 of Lecture Notes in Computer Science, page 642-659. Springer, (2022)Fully Distributed On-chip Instruction Memory Design for Stream Architecture Based on Field-Divided VLIW Compression.Y. He, M. Guan, C. Zhang, T. Tian, and Q. Yang. HPCC-ICESS, page 25-32. IEEE Computer Society, (2012)Tiled Multi-Core Stream Architecture.N. Wu, Q. Yang, M. Wen, Y. He, J. Ren, M. Guan, and C. Zhang. Trans. High Perform. Embed. Archit. Compil., (2011)Software Managed Instruction Scratchpad Memory Optimization in Stream Architecture Based on Hot Code Analysis of Kernels.Y. He, J. Ren, M. Wen, Q. Yang, N. Wu, and C. Zhang. DSD, page 823-830. IEEE Computer Society, (2010)Poster Abstract: A Template-based Framework for Generating Network Processor in FPGA.Z. Cao, H. Su, Q. Yang, M. Wen, and C. Zhang. INFOCOM Workshops, page 1057-1058. IEEE, (2019)

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Disambiguation of "Yang, Qianming"

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A Low-Cost Floating-Point Dot-Product-Dual-Accumulate Architecture for HPC-Enabled AI.

Please choose a person to relate this publication to

Yang Yang

Yang Yang

Yang Yang

Yang Yang

Yang Yang

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Yang, Qianming"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Low-Cost Floating-Point Dot-Product-Dual-Accumulate Architecture for HPC-Enabled AI.

Please choose a person to relate this publication to

Yang Yang

Yang Yang

Yang Yang

Yang Yang

Yang Yang

Other publications of authors with the same name

Disambiguation

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URL
DOI
BibTeX
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Chicago
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A Low-Cost Floating-Point Dot-Product-Dual-Accumulate Architecture for HPC-Enabled AI.