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Disambiguation of "Mandal, Chittaranjan"

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SamaTulyataOne: A Path Based Equivalence Checker.

, , and . ISEC, page 21:1-21:5. ACM, (2019)

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Chittaranjan Mohapatra

Chittaranjan Bhaduri

Chittaranjan Tripathy

Chittaranjan Barat

Avradip Mandal

 

Other publications of authors with the same name

Tensor-Based Rule-Space Management System in SDN., , , and . IEEE Syst. J., 13 (4): 3921-3928 (2019)CORE: Prediction-Based Control Plane Load Reduction in Software-Defined IoT Networks., , and . IEEE Trans. Commun., 69 (3): 1835-1844 (2021)Secure Path Balanced BDD-Based Pre-Charge Logic for Masking., , and . IEEE Trans. Circuits Syst., 67-I (12): 4747-4760 (2020)Aiding Teaching of Logic Design and Computer Organization through Dynamic Problem Generation and Automatic Checker Using COLDVL Tool., , , and . T4E, page 15-22. IEEE Computer Society, (2015)Path-Balanced Logic Design to Realize Block Ciphers Resistant to Power and Timing Attacks., , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (5): 1080-1092 (2019)CURE: Consistent Update With Redundancy Reduction in SDN., , , and . IEEE Trans. Commun., 66 (9): 3974-3981 (2018)A Value Propagation Based Equivalence Checking Method for Verification of Code Motion Techniques., , , and . ISED, page 67-71. IEEE, (2012)SamaTulyataOne: A Path Based Equivalence Checker., , and . ISEC, page 21:1-21:5. ACM, (2019)Deriving Bisimulation Relations from Path Extension Based Equivalence Checkers., , and . IEEE Trans. Software Eng., 43 (10): 946-953 (2017)DART: Data Plane Load Reduction for Traffic Flow Migration in SDN., , and . IEEE Trans. Commun., 69 (3): 1765-1774 (2021)