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Mix-GEMM: An efficient HW-SW Architecture for Mixed-Precision Quantized Deep Neural Networks Inference on Edge Devices.

E. Reggiani, A. Pappalardo, M. Doblas, M. Moretó, M. Olivieri, O. Unsal, and A. Cristal. HPCA, page 1085-1098. IEEE, (2023)

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Núria Gel Moretó

Miguel Moreto

Beate Miquel

Miquel Marqués

Joan Miquel

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Runtime-assisted cache coherence deactivation in task parallel programs.P. Caheny, L. Alvarez, M. Valero, M. Moretó, and M. Casas. SC, page 35:1-35:12. IEEE / ACM, (2018)Dynamic Cache Partitioning Based on the MLP of Cache Misses.M. Moretó, F. Cazorla, A. Ramírez, and M. Valero. Trans. High Perform. Embed. Archit. Compil., (2011)CPU Accounting in CMP Processors.C. Luque, M. Moretó, F. Cazorla, R. Gioiosa, A. Buyuktosunoglu, and M. Valero. IEEE Comput. Archit. Lett., 8 (1): 17-20 (2009)Adaptive Power Shifting for Power-Constrained Heterogeneous Systems.C. Ortega, L. Alvarez, A. Buyuktosunoglu, R. Bertran, T. Rosedahl, P. Bose, and M. Moretó. IEEE Trans. Computers, 72 (3): 627-640 (March 2023)On the use of many-core Marvell ThunderX2 processor for HPC workloads.V. Pardos, A. Armejach, D. Gracia, and M. Moretó. J. Supercomput., 77 (4): 3315-3338 (2021)Functional Verification of a RISC-V Vector Accelerator.V. Jiménez, M. Rodríguez, M. Domínguez, J. Sans, I. Diaz, L. Valente, V. Guglielmi, J. Quiroga, R. Genovese, N. Sönmez and 2 other author(s). IEEE Des. Test, 40 (3): 36-44 (June 2023)A Security Model for Randomization-based Protected Caches.J. Ribes-González, O. Farràs, C. Hernández, V. Kostalabros, and M. Moretó. IACR Cryptol. ePrint Arch., (2022)Evaluating Execution Time Predictability of Task-Based Programs on Multi-Core Processors.T. Grass, A. Rico, M. Casas, M. Moretó, and A. Ramírez. Euro-Par Workshops (2), volume 8806 of Lecture Notes in Computer Science, page 218-229. Springer, (2014)Evolutionary system for prediction and optimization of hardware architecture performance.P. Valdivieso, J. Guervós, M. Moretó, F. Cazorla, M. Valero, A. Mora, J. Laredo, and S. McKee. IEEE Congress on Evolutionary Computation, page 1941-1948. IEEE, (2008)Towards Reconfigurable Accelerators in HPC: Designing a Multipurpose eFPGA Tile for Heterogeneous SoCs.T. Hotfilter, F. Kreß, F. Kempf, J. Becker, J. Ruiz, D. Jiménez-González, M. Moretó, C. Álvarez, J. Labarta, and I. Baili. DATE, page 628-631. IEEE, (2022)

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Disambiguation of "Moretó, Miquel"

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Mix-GEMM: An efficient HW-SW Architecture for Mixed-Precision Quantized Deep Neural Networks Inference on Edge Devices.

Please choose a person to relate this publication to

Núria Gel Moretó

Miguel Moreto

Beate Miquel

Miquel Marqués

Joan Miquel

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Moretó, Miquel"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Mix-GEMM: An efficient HW-SW Architecture for Mixed-Precision Quantized Deep Neural Networks Inference on Edge Devices.

Please choose a person to relate this publication to

Núria Gel Moretó

Miguel Moreto

Beate Miquel

Miquel Marqués

Joan Miquel

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Mix-GEMM: An efficient HW-SW Architecture for Mixed-Precision Quantized Deep Neural Networks Inference on Edge Devices.