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A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Aerospace Applications.

, , , , , , and . IEEE Trans. Aerosp. Electron. Syst., 56 (4): 2666-2676 (2020)

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A high performance SEU-tolerant latch for nanoscale CMOS technology.. DATE, page 1-5. European Design and Automation Association, (2014)Single event double-upset fully immune and transient pulse filterable latch design for nanoscale CMOS., , , , and . Microelectron. J., (2017)A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Aerospace Applications., , , , , , and . IEEE Trans. Aerosp. Electron. Syst., 56 (4): 2666-2676 (2020)Method of generating strategic guidance information for driving evacuation flows to approach safety-based system optimal dynamic flows: Case study of a large stadium., , , , and . J. Systems Science & Complexity, 28 (3): 606-622 (2015)Design of Wireless Network on Chip with Priority-Based MAC., , , , , and . Journal of Circuits, Systems, and Computers, 28 (8): 1950124:1-1950124:18 (2019)A Novel Triple-Node-Upset-Tolerant CMOS Latch Design using Single-Node-Upset-Resilient Cells., , , , , , , , and . ITC-Asia, page 139-144. IEEE, (2019)CC-RTSV: Cross-Cellular Based Redundant TSV Design for 3D ICs., , , , , , , and . J. Circuits Syst. Comput., 29 (11): 2050144:1-2050144:19 (2020)Design Guidelines and Feedback Structure of Ring Oscillator PUF for Performance Improvement., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (1): 71-84 (January 2024)Cross-Layer Dual Modular Redundancy Hardened Scheme of Flip-Flop Design Based on Sense-Amplifier., , , , , , , and . J. Circuits Syst. Comput., 30 (5): 2120003:1-2120003:16 (2021)Novel Critical Gate-Based Circuit Path-Level NBTI-Aware Aging Circuit Degradation Prediction., , , , , , and . J. Circuits Syst. Comput., 32 (10): 2350175:1-2350175:19 (August 2023)