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Disambiguation of "Marongiu, Andrea"

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Design and Evaluation of SmallFloat SIMD extensions to the RISC-V ISA.

, , , , and . DATE, page 654-657. IEEE, (2019)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Federico Marongiu

Daniele Marongiu

Andrea Witzenrath

Risikofaktoren für abdominelle Komplikationen nach kardiopulmonalem Bypass. Uni Erlangen-Nürnberg, (2009)

Andrea Rottach

Analysis of the cell cycle dependent dynamics of Dnmt1 and Np95 in living cells. Uni München, (2009)

Andrea Hruby

Die MAPKKK Bck1p des Zellwand-Integritätssignalwegs in der Bäckerhefe Saccharomyces cerevisiae. Uni Münster, (2009)
 

Other publications of authors with the same name

Guest Editorial Energy-Quality Scalable Circuits and Systems for Sensing and Computing: From Approximate to Communication-Inspired and Learning-Based., , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (3): 361-368 (2018)Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms., , and . CASES, page 145-149. ACM, (2007)SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs., , , , , , and . CODES+ISSS, page 39-48. ACM, (2011)Exploring Single Source Shortest Path Parallelization on Shared Memory Accelerators., and . SCOPES, page 197-200. ACM, (2016)Taming Data Caches for Predictable Execution on GPU-based SoCs., , and . DATE, page 650-653. IEEE, (2019)Ultra low-power visual odometry for nano-scale unmanned aerial vehicles., , and . DATE, page 1647-1650. IEEE, (2017)Supporting OpenMP on a multi-cluster embedded MPSoC., , and . Microprocess. Microsystems, 35 (8): 668-682 (2011)The Predictable Execution Model in Practice: Compiling Real Applications for COTS Hardware., , , , and . ACM Trans. Embed. Comput. Syst., 20 (5): 47:1-47:25 (2021)Efficient OpenMP support and extensions for MPSoCs with explicitly managed memory hierarchy., and . DATE, page 809-814. IEEE, (2009)Combining PREM compilation and ILP scheduling for high-performance and predictable MPSoC execution., , , , , and . PMAM@PPoPP, page 11-20. ACM, (2018)