( en | de | ru )

 

Disambiguation of "Chu, Michael"

Author of the publication

copydeleteadd this publication to your clipboard
A four-bit full adder implemented on fast SiGe FPGAs with novel power control scheme.

, , , , , , , , and . FPGA, page 248. ACM, (2003)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Chu Duc

Xiaolan Chu

Chengcai Chu

Pakong Chu

Li Chu

 

Other publications of authors with the same name

Automated Detection of Under-Constrained Circuits in Zero-Knowledge Proofs., , , , , , , , , and . Proc. ACM Program. Lang., 7 (PLDI): 1510-1532 (2023)A 6.9 ns, 560 macrocell, in system programmable, CMOS PLD with 3.3-5 volt I/O capability., , , , , , , , , and 5 other author(s). CICC, page 265-268. IEEE, (1998)A High Speed Reconfigurable Gate Array for Gigahertz Applications., , , , , and . ISVLSI, page 124-129. IEEE Computer Society, (2005)A 11 GHz FPGA with Test Applications., , , , , and . FPL, page 101-105. IEEE, (2005)Gigahertz FPGA by SiGe BiCMOS Technology for Low Power, High Speed Computing with 3-D Memory., , , , , , , , , and . FPL, volume 2778 of Lecture Notes in Computer Science, page 11-20. Springer, (2003)Design of BiCMOS SRAMs for high-speed SiGe applications., , , , , , , , and . IET Circuits Devices Syst., 8 (6): 487-498 (2014)52 Gb/s 16: 1 transmitter in 0.13 μm SiGe BiCMOS technology., , , , and . IET Circuits Devices Syst., 1 (6): 427-432 (2007)A four-bit full adder implemented on fast SiGe FPGAs with novel power control scheme., , , , , , , , and . FPGA, page 248. ACM, (2003)The 10GHz 4: 1 MUX and 1: 4 DEMUX implemented via the gigahertz SiGe FPGA., , , , , , , , and . ACM Great Lakes Symposium on VLSI, page 141-144. ACM, (2004)Hybrid transactional memory., , , , and . PPoPP, page 209-220. ACM, (2006)