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Memory fartitioning-based modulo scheduling for high-level synthesis., , , , , and . ISCAS, page 1-4. IEEE, (2017)Hierarchical representation of on-chip context to reduce reconfiguration time and implementation area for coarse-grained reconfigurable architecture., , , , , , and . Sci. China Inf. Sci., 56 (11): 1-20 (2013)Implementation of AVS Jizhun decoder with HW/SW partitioning on a coarse-grained reconfigurable multimedia system., , , , , and . Sci. China Inf. Sci., 57 (8): 1-14 (2014)Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (5): 1895-1908 (2016)Energy Management on Battery-Powered Coarse-Grained Reconfigurable Platforms., , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (12): 3085-3098 (2015)Hybrid circuit-switched network for on-chip communication in large-scale chip-multiprocessors., , , and . J. Parallel Distributed Comput., 74 (9): 2818-2830 (2014)A Cycle-Accurate Simulator for a Reconfigurable Multi-Media System., , , , and . IEICE Trans. Inf. Syst., 93-D (12): 3202-3210 (2010)Low-Power Loop Parallelization onto CGRA Utilizing Variable Dual VDD., , , and . IEICE Trans. Inf. Syst., 98-D (2): 243-251 (2015)A 2.69 Mbps/mW 1.09 Mbps/kGE Conjugate Gradient-based MMSE Detector for 64-QAM 128×8 Massive MIMO Systems., , , , , and . A-SSCC, page 191-194. IEEE, (2018)Reconfigurable computing - evolution of Von Neumann architecture.. FPT, IEEE, (2010)