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Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip.

, , , , , and . ICCD, page 494-499. IEEE Computer Society, (2002)

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A hierarchical multi-level test generation system., and . Great Lakes Symposium on VLSI, page 54-59. IEEE, (1991)Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting., , , , , and . IEEE Trans. Computers, 48 (8): 769-779 (1999)Energy-performance tradeoffs for the shared memory in multi-processor systems-on-chip., , and . ISCAS (2), page 361-364. IEEE, (2004)Telescopic Units: Increasing the Average Throughput of Pipelined Designs by Adaptive Latency Control., , and . DAC, page 22-27. ACM Press, (1997)Kernel-Based Power Optimization of RTL Components: Exact and Approximate Extraction Algorithms., , , , and . DAC, page 247-252. ACM Press, (1999)Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques., , , , and . DAC, page 467-470. ACM Press, (1996)Pass-XNOR logic: A new logic style for P-N junction based graphene circuits., , , and . DATE, page 1-4. European Design and Automation Association, (2014)Fine-Grain Back Biasing for the Design of Energy-Quality Scalable Operators., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (6): 1042-1055 (2019)A Layered Methodology for the Simulation of Extra-Functional Properties in Smart Systems., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (10): 1702-1715 (2017)Symbolic optimization of interacting controllers based onredundancy identification and removal., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (7): 760-772 (2000)