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Architecture-Level Exploration of Alternative Interconnection Schemes Targeting 3D FPGAs: A Software-Supported Methodology., , and . Int. J. Reconfigurable Comput., (2008)A novel methodology for designing high-performance and low-energy FPGA routing architecture., , , and . FPGA, page 224. ACM, (2006)NAROUTO: An open-source framework for supporting architecture-level exploration at heterogeneous FPGAS., , and . ICECS, page 527-530. IEEE, (2010)A virtual platform for exploring hierarchical interconnection for many-accelerator systems., , , and . SAMOS, page 384-389. IEEE, (2015)Rapid prototyping and Design Space Exploration methodologies for many-accelerator systems., , , , and . FPL, page 1-2. IEEE, (2015)Automated Design Approximation to Overcome Circuit Aging., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (11): 4710-4721 (2021)Dynamic Memory Management in Vivado-HLS for Scalable Many-Accelerator Architectures., , , and . ARC, volume 9040 of Lecture Notes in Computer Science, page 117-128. Springer, (2015)SPARTAN/SEXTANT/COMPASS: Advancing Space Rover Vision via Reconfigurable Platforms., , , , , , , , , and 3 other author(s). ARC, volume 9040 of Lecture Notes in Computer Science, page 475-486. Springer, (2015)Hardware-Aware Automated Neural Minimization for Printed Multilayer Perceptrons., , , , and . DATE, page 1-2. IEEE, (2023)AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow., , , , , , , , , and 1 other author(s). ASP-DAC, page 3-4. ACM Press, (2005)